1. Technical Field
Various embodiments generally relate to a reservoir capacitor, and more particularly, to a semiconductor apparatus including a reservoir capacitor.
2. Related Art
In general, a semiconductor apparatus such as DRAM (Dynamic Random Access Memory) includes stabilization capacitors called reservoir capacitors and arranged in a spare area of a peripheral area adjacent to a memory block, in order to stabilize a voltage from noise.
As the reservoir capacitor, a transistor type structure using a MOS transistor manufacturable using a CMOS (Complementary Metal-Oxide Semiconductor) process, and a well type structure using a well have been extensively used.
The transistor type reservoir capacitor includes a gate dielectric layer formed on a substrate, a gate formed on the gate dielectric layer, and a source and a drain formed in a well exposed at both sides of the gate.
A voltage, which is equal to or more than a threshold value tolerable by the gate dielectric layer, may be applied to the reservoir capacitor. As described above, when the voltage, which is equal to or more than the threshold value tolerable by the gate dielectric layer, is applied, the gate may be damaged. When the gate is damaged, since a current path from the gate to the substrate is formed, a semiconductor apparatus may fail.
In this regard, in order to install the reservoir capacitor to which a voltage higher than the threshold value of the gate dielectric layer is applied, a plurality of MOS capacitors may be used because the semiconductor apparatus may fail because of one MOS capacitor. Particularly, as illustrated in FIG. 1 and FIG. 2, it is preferable to serially couple MOS capacitors to each other. FIG. 1 is a circuit diagram of a conventional 2-stage serial MOS capacitor and FIG. 2 is an equivalent circuit diagram of FIG. 1.
Each MOS capacitor may include a gate-source capacitor, a gate-body (bulk) capacitor, and a gate-drain capacitor, that is, three parallel capacitors cgs, cgb, and cgd. When it is assumed that the sizes of the MOS capacitors are substantially equal to one another, a voltage of 1/n is applied to each MOS capacitor (where n may be a non-negative integer).
FIG. 3 is a layout diagram of a conventional reservoir capacitor.
As illustrated in FIG. 1 to FIG. 3, the reservoir capacitor may include a first MOS capacitor 10, and a second MOS capacitor 20 serially coupled to the first MOS capacitor 10. The first MOS capacitor 10 being coupled to a high voltage level and the second MOS capacitor 20 being coupled between the first MOS capacitor 10 and a ground voltage VSS.
Referring to FIG. 3, the first MOS capacitor 10 is arranged in a first area 10a and the second MOS capacitor 20 is arranged in a second area 20a. For example, the first area 10a may be an R-type well. The first area 10a may be surrounded by a N-type well 2. The first MOS capacitor 10 includes a first gate 11, a first source 13, and a first drain 15. Accordingly a gate-source capacitor cgs1 may be generated between the first source 13 and the first gate 11, a gate-bulk capacitor cgb1 may be generated between the first gate 11 and the first area 10a, and a gate-drain capacitor cgd1 may be generated between the first drain 15 and the first gate 11. The capacitors cgs1, cgb1 and cgd1 may be formed in parallel with one another as described above.
The second area 20a may be a P-type silicon substrate 1. The second MOS capacitor 20 includes a second gate 21, a second source 23 and a second drain 25. Accordingly, a gate-source capacitor cgs2 may be generated between the second source 23 and the gate 21, a gate-bulk capacitor cgb2 may be generated between the second gate 21 and the second area 20a, and a gate-drain capacitor cgd2 may be generated between the second drain 25 and the second gate 21. The capacitors cgs2, cgb2 and cgd2 may be formed in parallel with one another, similarly to the first MOS capacitor 10.
The first gate 11 is connected to a voltage terminal which may be inputted with a high voltage. The second gate 21 is connected to the first source 13 and the first drain 15, in common. The second source 23 and the second drain 25 are connected to the ground voltage terminal VSS, in common.
However, respective MOS capacitors constituting the reservoir capacitor are formed in wells different from each other, resulting in an increase in the occupation area of the semiconductor apparatus.